1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a control for isolating a bit line and a sense amplifier from each other in a dynamic random access memory (DRAM) having a shared sense amplifier configuration.
2. Description of the Background Art
Reduction in power consumption is being demanded in a DRAM when the DRAM is mounted to a battery driven device. In the case where the DRAM has a shared sense amplifier configuration, by fixing a bit line isolation signal while the same memory block is refreshed, at the time of self refresh of a DRAM, charge/discharge current of a gate for isolating the shared sense amplifier from the memory block can be reduced.
For example, FIGS. 14 and 15 of Japanese Patent Laying-Open No. 9-161477 show the configuration that an output C8 of a specific digit of a refresh counter is used and, during self refresh, only when C8 changes, a bit line isolation signal BLI is changed.
However, in a DRAM, the configuration of a memory cell array has to be often changed. Particularly, in a system LSI having therein a DRAM as a block (also referred to as an embedded DRAM), in many cases, the configuration of a memory cell array has to be changed according to the system installed.
When the charge/discharge current is reduced by the conventional method of controlling bit line isolation signal BLI in accordance with a specific digit of a refresh counter, inconvenience is caused at the time of changing the configuration of the memory cell array.
Specifically, each time the configuration of the memory cell array is changed, the corresponding relation between the digit of an address signal and the row and column of the memory cell array changes. Consequently, at the time of realizing various array configurations, the digit of a self refresh counter to be referred to changes and a problem arises such that the layout pattern of a circuit has to be changed.
In the conventional configuration, in a normal mode, even in the case of successively accessing only the same memory block, bit line signal BLI is changed every cycle bit. Consequently, there is also a problem such that unnecessary charge/discharge current flows even in a normal operation mode and the power consumption is large.